The semiconductor has been developing for the four decades since the birth of the first semiconductor device. For performing more complicated operations at a higher speed, more and more devices and connections are formed within a circuit. The density of semiconductor chips is raised to include more devices and functions in a single chip. In the integrated circuit, a great number of devices and connections are fabricated on a single chip. Various kinds of devices like transistors, resistors, and capacitors are formed together. Each device must operate with good connections to provide interaction between each other for completing the functionality, especially under the higher and higher packing density of the integrated circuits.
Connections must be formed in addition to these densely arranged devices for finishing a circuit to perform operations. In the semiconductor manufacturing process, metallization is a process to form connections between devices. With more and more devices on a chip with high integrity, the early stage single layer metallization process had been improved to form multiple layers of connections. Two layers, three layers, or even four layers of connections are formed in present applications. With the sub-micrometer or even smaller devices, the metallization process is challenged with forming narrower conductive lines with compromising resistance. More layers of connections must be formed with low misalignment and good yield.
For fabricating high density devices like ULSI (ultra-large scale integration) devices, metallization with small pitch and a multilevel-structure becomes necessary for providing high packing density with reliable functionality. D. Butler disclosed an analysis of several metallization techniques in the article "Options for Multilevel Metallization" in Solid State Technology p. s7, March, 1996. He disclosed that fundamental limitations in the performance of established metallization technologies become increasingly apparent for smaller feature size of the devices. Higher packing density has led to additional levels of metal interconnects. It is possible to use up to four to six levels of interconnects in the design rule for logic devices with 0.35 micrometer feature size. The metallization process needs to be improved for providing connections with higher operating speeds, reduced RC delay, and increased reliability. A comparison between several metallization technologies including aluminum reflow, tungsten plug, and forcefill aluminum are provided in his work.
In the conventional planarization process for metallization, several problems hindered the application for high integrity circuits. Problems like the interlevel dielectric gap fill and subsequent local or global planarization are difficult to overcome even with the chemical-mechanical polishing (CMP) technology. In the work of K. Kikuta et al. in "Multilevel Planarized-Trench-Aluminum (PTA) Interconnection Using Reflow Sputtering and Chemical Mechanical Polishing" (in IEDM Tech. Dig. P. 285, 1993), these challenges are addressed. The electrode pitch has become smaller as the packing density of devices increases. Multilevel-metallization has become necessary for densely arranged devices. Dielectric planarization has been developed for high density devices with multilevel interconnection. The conventional planarization problems of interlevel dielectric gap fill and subsequent local or global planarization are also emphasized. A metal planarization for achieving borderless or self-aligned contacts with minimum line pitch is also disclosed in the work.
In recent times, the damascene technology has been reported to achieve the metal planarization with self-aligned contact and minimum line pitch. A damascene structure to form high-density interconnect wiring is presented by R. V. Joshi in the work "A New Damascene Structure for Submicrometer Interconnect Wiring" in IEEE Electron Device Letters, vol. 14, No. 3, 1993. The structure results in improved short yields, lower sheet resistances, comparable contact/via resistances, and shows excellent filling of high-aspect-ratio long lines with high copper content compared to traditionally used wiring fabricated by reactively ion etching (RIE) of Ti/Al--Cu/Ti/TiN.
However, for multilevel-metallization, in conventional damascene technology it is also difficult to control the pattern misalignment problem. In U.S. Pat. No. 5,598,027 to M. Matsuura for "Semiconductor Device and Method of Fabricating the same", the pattern misregistration in forming a multilayer interconnection structure is illustrated. The problem causes circuit short and element damages and thus yield of the process is reduced. For fabricating integrated circuits with high packing density, a metallization process solving the problem of planarization and misalignment must be developed.